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misc: Replace references to IntPtr/UIntPtr with nint/nuint + code cleanups.

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This commit is contained in:
Evan Husted
2024-10-26 08:46:41 -05:00
parent a09d314817
commit dfb4854d19
172 changed files with 902 additions and 914 deletions
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2
src/Ryujinx.Cpu/LightningJit/Arm64/A64Compiler.cs
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@@ -13,7 +13,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
IMemoryManager memoryManager,
ulong address,
AddressTable<ulong> funcTable,
IntPtr dispatchStubPtr,
nint dispatchStubPtr,
Architecture targetArch)
{
if (targetArch == Architecture.Arm64)

10
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Compiler.cs
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@@ -20,11 +20,11 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
public readonly RegisterAllocator RegisterAllocator;
public readonly TailMerger TailMerger;
public readonly AddressTable<ulong> FuncTable;
public readonly IntPtr DispatchStubPointer;
public readonly nint DispatchStubPointer;
private readonly MultiBlock _multiBlock;
private readonly RegisterSaveRestore _registerSaveRestore;
private readonly IntPtr _pageTablePointer;
private readonly nint _pageTablePointer;
public Context(
CodeWriter writer,
@@ -33,8 +33,8 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
RegisterSaveRestore registerSaveRestore,
MultiBlock multiBlock,
AddressTable<ulong> funcTable,
IntPtr dispatchStubPointer,
IntPtr pageTablePointer)
nint dispatchStubPointer,
nint pageTablePointer)
{
Writer = writer;
RegisterAllocator = registerAllocator;
@@ -304,7 +304,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
}
}
public static CompiledFunction Compile(CpuPreset cpuPreset, IMemoryManager memoryManager, ulong address, AddressTable<ulong> funcTable, IntPtr dispatchStubPtr)
public static CompiledFunction Compile(CpuPreset cpuPreset, IMemoryManager memoryManager, ulong address, AddressTable<ulong> funcTable, nint dispatchStubPtr)
{
MultiBlock multiBlock = Decoder.DecodeMulti(cpuPreset, memoryManager, address);

16
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitSystem.cs
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@@ -144,27 +144,27 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
return name == InstName.Svc;
}
private static IntPtr GetBrkHandlerPtr()
private static nint GetBrkHandlerPtr()
{
return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.Break);
}
private static IntPtr GetSvcHandlerPtr()
private static nint GetSvcHandlerPtr()
{
return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.SupervisorCall);
}
private static IntPtr GetUdfHandlerPtr()
private static nint GetUdfHandlerPtr()
{
return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.Undefined);
}
private static IntPtr GetCntpctEl0Ptr()
private static nint GetCntpctEl0Ptr()
{
return Marshal.GetFunctionPointerForDelegate<Get64>(NativeInterface.GetCntpctEl0);
}
private static IntPtr CheckSynchronizationPtr()
private static nint CheckSynchronizationPtr()
{
return Marshal.GetFunctionPointerForDelegate<GetBool>(NativeInterface.CheckSynchronization);
}
@@ -215,7 +215,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
TailMerger tailMerger,
Action writeEpilogue,
AddressTable<ulong> funcTable,
IntPtr dispatchStubPtr,
nint dispatchStubPtr,
InstName name,
ulong pc,
uint encoding,
@@ -298,7 +298,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
TailMerger tailMerger,
Action writeEpilogue,
AddressTable<ulong> funcTable,
IntPtr funcPtr,
nint funcPtr,
int spillBaseOffset,
ulong pc,
Operand guestAddress,
@@ -369,7 +369,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
private static void WriteCall(
ref Assembler asm,
RegisterAllocator regAlloc,
IntPtr funcPtr,
nint funcPtr,
int spillBaseOffset,
int? resultRegister,
params ulong[] callArgs)