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Add SMULL (vector), USHR (scalar), FCCMPE, FNMSUB, fixed a some instructions

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This commit is contained in:
gdkchan
2018-02-20 14:39:03 -03:00
parent 01b7538560
commit b4a1cfde10
10 changed files with 205 additions and 130 deletions
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29
Ryujinx/Cpu/Instruction/AInstEmitBfm.cs
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@@ -36,7 +36,7 @@ namespace ChocolArm64.Instruction
if (Op.Pos + 1 == BitsCount)
{
EmitBfmShift(Context, OpCodes.Shr);
EmitSbfmShift(Context);
}
else if (Op.Pos < Op.Shift)
{
@@ -87,7 +87,7 @@ namespace ChocolArm64.Instruction
if (Op.Pos + 1 == Op.GetBitsCount())
{
EmitBfmShift(Context, OpCodes.Shr_Un);
EmitUbfmShift(Context);
}
else if (Op.Pos < Op.Shift)
{
@@ -166,19 +166,28 @@ namespace ChocolArm64.Instruction
Context.EmitStintzr(Op.Rd);
}
private static void EmitBfmShift(AILEmitterCtx Context, OpCode ILOp)
private static void EmitSbfmShift(AILEmitterCtx Context)
{
EmitBfmShift(Context, true);
}
private static void EmitUbfmShift(AILEmitterCtx Context)
{
EmitBfmShift(Context, false);
}
private static void EmitBfmShift(AILEmitterCtx Context, bool Signed)
{
AOpCodeBfm Op = (AOpCodeBfm)Context.CurrOp;
if (Op.Shift > 0)
{
Context.EmitLdintzr(Op.Rn);
Context.EmitLdc_I4(Op.Shift);
Context.EmitLdintzr(Op.Rn);
Context.EmitLdc_I4(Op.Shift);
Context.Emit(ILOp);
Context.Emit(Signed
? OpCodes.Shr
: OpCodes.Shr_Un);
Context.EmitStintzr(Op.Rd);
}
Context.EmitStintzr(Op.Rd);
}
private static void EmitBfmLsl(AILEmitterCtx Context)