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a79b39b91347816ea14677b58af738b70df03e9c
ryujinx-mirror/ARMeilleure/Instructions
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gdkchan ab9d4b862d Implement VORN (register) Arm32 instruction (#2396)
2021-06-23 23:21:23 +02:00
..
CryptoHelper.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
InstEmitAlu32.cs
Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)
2020-12-17 20:43:41 +01:00
InstEmitAlu.cs
Add most of the A32 instruction set to ARMeilleure (#897)
2020-02-24 08:20:40 +11:00
InstEmitAluHelper.cs
Clear JIT cache on exit (#1518)
2020-12-16 17:07:42 -03:00
InstEmitBfm.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
InstEmitCcmp.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
InstEmitCsel.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
InstEmitDiv.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
InstEmitException32.cs
IPC refactor part 1: Use explicit separate threads to process requests (#1447)
2020-09-22 14:50:40 +10:00
InstEmitException.cs
IPC refactor part 1: Use explicit separate threads to process requests (#1447)
2020-09-22 14:50:40 +10:00
InstEmitFlow32.cs
Generalize tail continues (#1298)
2020-06-18 13:37:21 +10:00
InstEmitFlow.cs
Generalize tail continues (#1298)
2020-06-18 13:37:21 +10:00
InstEmitFlowHelper.cs
Add multi-level function table (#2228)
2021-05-29 18:06:28 -03:00
InstEmitHash32.cs
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
2020-07-13 20:48:14 +10:00
InstEmitHash.cs
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
2020-07-13 20:48:14 +10:00
InstEmitHashHelper.cs
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
2020-07-13 20:48:14 +10:00
InstEmitHelper.cs
Clear JIT cache on exit (#1518)
2020-12-16 17:07:42 -03:00
InstEmitMemory32.cs
Add most of the A32 instruction set to ARMeilleure (#897)
2020-02-24 08:20:40 +11:00
InstEmitMemory.cs
Fold constant offsets and group constant addresses (#2285)
2021-05-13 21:26:57 +02:00
InstEmitMemoryEx32.cs
Implement inline memory load/store exclusive and ordered (#1413)
2020-07-30 11:29:28 -03:00
InstEmitMemoryEx.cs
Implement PRFM (register variant) as NOP (#1956)
2021-01-26 16:09:27 +11:00
InstEmitMemoryExHelper.cs
Validate CPU virtual addresses on access (#1987)
2021-02-16 19:04:19 +01:00
InstEmitMemoryHelper.cs
Add multi-level function table (#2228)
2021-05-29 18:06:28 -03:00
InstEmitMove.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
InstEmitMul32.cs
Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)
2020-12-17 20:43:41 +01:00
InstEmitMul.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
InstEmitSimdArithmetic32.cs
Implement VCNT instruction (#1963)
2021-02-22 16:26:13 +01:00
InstEmitSimdArithmetic.cs
Improve accuracy of reciprocal step instructions (#2305)
2021-05-24 20:20:07 +10:00
InstEmitSimdCmp32.cs
CPU: This PR fixes Fpscr, among other things. (#1433)
2020-08-08 17:18:51 +02:00
InstEmitSimdCmp.cs
CPU: This PR fixes Fpscr, among other things. (#1433)
2020-08-08 17:18:51 +02:00
InstEmitSimdCrypto32.cs
Add Profiled Persistent Translation Cache. (#769)
2020-06-16 20:28:02 +02:00
InstEmitSimdCrypto.cs
Add Profiled Persistent Translation Cache. (#769)
2020-06-16 20:28:02 +02:00
InstEmitSimdCvt32.cs
CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)
2020-12-16 20:27:15 -03:00
InstEmitSimdCvt.cs
CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Now HardwareCapabilities uses CpuId. (#1650)
2020-11-18 19:35:54 +01:00
InstEmitSimdHash.cs
Add Profiled Persistent Translation Cache. (#769)
2020-06-16 20:28:02 +02:00
InstEmitSimdHelper32.cs
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
2021-01-04 23:45:54 +01:00
InstEmitSimdHelper.cs
Add BIC/ORR Vd.T, #imm fast path (#2279)
2021-05-20 09:09:17 -03:00
InstEmitSimdLogical32.cs
Implement VORN (register) Arm32 instruction (#2396)
2021-06-23 23:21:23 +02:00
InstEmitSimdLogical.cs
Add BIC/ORR Vd.T, #imm fast path (#2279)
2021-05-20 09:09:17 -03:00
InstEmitSimdMemory32.cs
Add most of the A32 instruction set to ARMeilleure (#897)
2020-02-24 08:20:40 +11:00
InstEmitSimdMemory.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
InstEmitSimdMove32.cs
Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471)
2020-08-13 02:34:02 -03:00
InstEmitSimdMove.cs
Add Profiled Persistent Translation Cache. (#769)
2020-06-16 20:28:02 +02:00
InstEmitSimdShift32.cs
Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). (#1577)
2020-10-13 22:41:33 +02:00
InstEmitSimdShift.cs
Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)
2020-07-13 21:08:47 +10:00
InstEmitSystem32.cs
CPU: This PR fixes Fpscr, among other things. (#1433)
2020-08-08 17:18:51 +02:00
InstEmitSystem.cs
Add Profiled Persistent Translation Cache. (#769)
2020-06-16 20:28:02 +02:00
InstName.cs
Implement VORN (register) Arm32 instruction (#2396)
2021-06-23 23:21:23 +02:00
NativeInterface.cs
Add multi-level function table (#2228)
2021-05-29 18:06:28 -03:00
SoftFallback.cs
Implement VCNT instruction (#1963)
2021-02-22 16:26:13 +01:00
SoftFloat.cs
Add Profiled Persistent Translation Cache. (#769)
2020-06-16 20:28:02 +02:00